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SiLabs aims at 56Gbit/s comms with low-jitter clock chips

Posted on June 26, 2018 by

Silicon Labs is aiming at 56Gbit/s PAM-4 serdes and 112Gbit/s serial applications with a set of clock generators, jitter attenuating clocks and voltage-controlled crystal oscillators. […]

Read the original post by Steve Bush

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